Tien-Sheng Chao – NYCU Electrophysics

1988 - 1992

Ph. D. Institute of Electronics Engineering, NCTU, Taiwan

1987 - 1988

M. S. Institute of Electronics Engineering, NCTU, Taiwan

1981 - 1985

B. S. Dept. of Electrical and Electronics Engineering, NCTU, Taiwan

2021/02 -

Professor, Department of Electrophysics, National Yang Ming Chiao Tung University

2009/08 - 2011/07

Chairman, Department of Electrophysics, National Chiao Tung University

2002/08 - 2021/01

Professor, Dept. Of Electrophysics, National Chiao Tung University

2001/08 - 2002/07

Associate Professor, Dept. Of Electrophysics, National Chiao Tung University

1992 - 2001

Associate Researcher / Researcher, National Nano Device Labs

Physics of Semiconductor Devices
Thin Films Deposition Techniques
ULSI Technology
Deep-Submicron Devices Fabrications
Ultra-thin Oxide Preparations
Ultra-clean Processes.

Y. Lee, C. C. Lee, Y. S. Kuo, S. W. Li, and T. S. Chao*, “Ultrathin Sub-5-nm Hf1-xZrxO2 for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate,” IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 9, pp. 236-241, 2021.
S. Kuo, S. Y. Lee, C. C. Lee, S. W. Li, T. S. Chao*, “CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications,” IEEE TRANSACTIONS ON ELECTRON DEVICES, 68(2), pp. 879-884, 2021.
H. Shen, W. Y. Chen, S. Y. Lee, P. Y. Kuo, and T. S. Chao*, “Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs,” IEEE TRANSACTIONS ON NANOTECHNOLOGY, 19, pp.322-327, 2020.
Y. Lee, H. W. Chen, C. H. Shen, P. Y. Kuo, C. C. Chung, Y. E. Huang, H. Y. Chen, and T. S. Chao*, “Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs,” IEEE Trans. On Electron Devices, 67 (2), pp. 711-716, 2020.
Y. Lee, H. W. Chen, C. H. Shen, P. Y. Kuo, C. C. Chung, Y. .E. Huang, H. Y. Chen, T. S. Chao* , ” Experimental Demonstration of Stacked Gate-All-Around Poly-Si Nanowires Negative Capacitance FETs with Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process,” IEEE Electron Device Letters, 40 (11), 1708-1711, 2019.
C. Chung, C. M. Ko, and T. S. Chao*, “Self -Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors,” IEEE J. OF the Electron Devices Society, 7, 959-963, 2019.
R. Hsieh, K. C. Lin, and T. S. Chao*, ” Investigation of Nitrous Oxide Nitridation Temperatures on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode TFTs,” IEEE J. OF the Electron Devices Society, 7(1), pp. 282-286, 2019.
Y. Lin, C. Y. Tsai, C. H. Shen, C. C. Chung, M. P. V. Kumar, and T. S. Chao*,”Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations,” IEEE Electron Dev. Letters, 39(9), pp.1326-1329, 2018.
P. V. Kumar, Y. J. Lin, K. H. Kao, and T. S. Chao*, “Junctionless FETs With a Fin Body for Multi-V-TH and Dynamic Threshold Operation,” IEEE Trans. On Electron Devices, 65 (8), pp. 3535-3542, 2018.
H. Shen, P. Y. Kuo, C. C. Chung, S. Y. Lee, and T. S. Chao*, “Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity,” IEEE Electron Dev. Letters, 39(4), pp.512-515, 2018.
Chris C. C. Chung, C. H. Shen, J. Y. Lin, C. C. Chin, and S. Chao*, “Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit,” IEEE Trans. On Electron Devices, 65 (2), pp. 756-762, 2018.
R. Hsieh, Y. D. Chan, P. Y. Kuo, and T. S. Chao*, “Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs,” IEEE J. of The Electron Dev. Soc., 6(1), pp. 314-319, 2018.
Y. Lin, M. P. V. Kumar, and T. S. Chao*, “Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability,” IEEE Electron Dev. Letters, 39(1), pp.8-11, 2018.