Chun-Jung Su
Associate Professor
Ph.D., Institute of Electronics, NCTU
Science Building III, SC 310
(03)5712121 #56150
Supreme Exploratory Nanoelectronics Lab.
Science Building III, SC 758
2002 - 2008
Ph.D., Institute of Electronics, NCTU
1998 - 2002
Bachelor, Department of Materials Science and Engineering, NCTU
2022/02 - 2022
Associate Professor, Department of Electrophysics, National Yang Ming Chiao Tung University
2019/01 - 2022/02
Researcher, Taiwan Semiconductor Research Institute
2015/11 - 2015/12
Visiting Scholar, School of Electrical and Computer Engineering, Purdue University, U.S.A.
2014/09 - 2018/12
Associate Researcher, National Nano Device Labs.
2013/01 - 2014/09
Principal Engineer, tsmc
2011/08 - 2012/12
Assitant Researcher, National Chiao Tung University
2009/01 - 2011/07
Postdoctor, National Chiao Tung University
2007/09 - 2008/08
Visiting Scholar, Institute of Semiconductor Electronics, RWTH Aachen University, Germany
2000/07 - 2000/08
Visiting Scholar, Texas Center for Superconductivity, University of Houston, U.S.A.
  1. Nanoelectronic device technology
  2. Semiconductor device and physics
  3. Non-volatile memory devices
  4. ALD thin-film deposition technology
  1. Design and fabrication of nanoelectronic devices
  2. Ferroelectric transistors: low-power logic and memory devices
  3. 2D materials: film synthesis and device fabrication
  4. Integration of 3D vertically-stacked devices
  5. Investigation on HK/MG and interface
  6. Emerging non-volatile memory technology
  1. C. H. Wu, K. C. Wang, Y. Y. Wang, T. L. Wu, C. J. Su*, and C. Hu “Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode,” Nanomaterials 12, 468 (2022)
  2. Y. J. Lin, C. Y. Teng, C. Hu, C. J. Su* and Y. C. Tseng, “Impacts of Surface Nitridation on Crystalline Ferroelectric Phase of Hf1-xZrxO2 and Ferroelectric FET Performance,” Appl. Phys. Lett. 119, 192102 (2021)
  3. C. J. Su*, M. K. Huang, K. S. Lee, V. P. H. Hu, Y. F. Huang, B. C. Zheng, C. H. Yao, N. C. Lin, K. H. Kao, T. C. Hong, P. J. Sung, C. T. Wu, T. Y. Yu, K. L. Lin, Y. C. Tseng, C. L. Lin, Y. J. Lee, T. S. Chao, J. Y. Li, W. F. Wu, J. M. Shieh, Y. H. Wang and W. K. Yeh, “3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers,” Tech. Digest IEDM, 12.2, San Francisco, December 12-16 (2020)
  4. Y. J. Lin, C. Y. Teng, S. J. Chang, Y. F. Liao, C. Hu, C. J. Su*, and Y. C. Tseng, “Role of Electrode-induced Oxygen Vacancies in Regulating Ferroelectric Wake-up in TiN/Hf0.5Zr0.5O2 Capacitors,” Appl. Surf. Sci. 528, 147014 (2020)
  5. Y. H. Chen, C. J. Su*, T. H. Yang, C. Hu, and T. L. Wu, “Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies using NH3 Plasma Treatment and Microwave Annealing,” IEEE Trans. Electron Device 67, 1581 (2020)
  6. T. H. Yang, C. J. Su*, Y. S. Wang, K. H. Kao, Y. J. Lee, T. L. Wu, “Impact of the Polarization on Time-Dependent Dielectric Breakdown in Ferroelectric Hf0.5Zr0.5O2 on Ge Substrates,” Jpn. J. Appl. Phys. 59, SGGB08 (2020)
  7. M. Si, C. J. Su, C. Jiang, N. Conrad, H. Zhou, K. Maize, G. Qiu, C. T. Wu, A. Shakouri, M. Alam, and P. D. Ye, “Steep Slope Hysteresis-free Negative Capacitance MoS2 Transistors,” Nature Nanotechnology, 13, 24 (2018)
  8. Y. T. Tang, C. J. Su*, Y. S. Wang, K. H. Kao, T. L. Wu, P. J. Sung, F. J. Hou, C. J. Wang, M. S. Yeh, Y. J. Lee, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, and Y. H. Wang, “A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node,” VLSI Symp., T5-1, Honolulu, June 18-22 (2018)
  9. C. J. Su*, T. C. Hong, Y. C. Tsou, F. J. Hou, P. J. Sung, M. S. Yeh, C. C. Wan, K. H. Kao, Y. T. Tang, C. H. Chiu, C. J. Wang, S. T. Chung, T. Y. You, Y. C. Huang, C. T. Wu, K. L. Lin, G. L. Luo, K. P. Huang, Y. J. Lee, T. S. Chao, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, and Y. H. Wang, “Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability,” Tech. Digest IEDM, 15.4, San Francisco, December 2-6 (2017)
  10. C. J. Su, Y. T. Tang, Y. C. Tsou, P. J. Sung, F. J. Hou, C. J. Wang, S. T. Chung, C. Y. Hsieh, Y. S. Yeh, F. K. Hsueh, K. H. Kao, S. S. Chuang, C. T. Wu, T. Y. You, Y. L. Jian, T. H. Chou, Y. L. Shen, B. Y. Chen, G. L. Luo, T. C. Hong, K. P. Huang, M. C. Chen, Y. J. Lee, T. S. Chao, T. Y. Tseng, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, and Y. H. Wang, “Nano-scaled Ge FinFETs with Low Temperature Ferroelectric HfZrOx on Specific Interfacial Layers Exhibiting 65% S.S. Reduction and Improved ION,” VLSI Symp., T12-1, Kyoto, Japan, June 5-8 (2017)
  11. C. J. Su*, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao, “Gate-all-around Junctionless Transistors with Heavily Doped Polysilicon Nanowire Channels,” IEEE Electron Device Lett., 32, 521 (2011) (Highly cited)